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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Designer'sTM Data Sheet
HDTMOS E-FET.TM High Energy Power FET D2PAK for Surface Mount
N-Channel Enhancement-Mode Silicon Gate
The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This advanced high-cell density HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Short Heatsink Tab Manufactured -- Not Sheared * Specially Designed Leadframe for Maximum Power Dissipation * Available in 24 mm 13-inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage -- Continuous Drain Current -- Continuous Drain Current -- Continuous @ 100C Drain Current -- Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (minimum footprint, FR-4 board) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = 25 V, VGS = 10 V, Peak IL = 75 A, L = 0.177 mH, RG = 25 ) Thermal Resistance -- Junction to Case Thermal Resistance -- Junction to Ambient Thermal Resistance -- Junction to Ambient (minimum footprint, FR-4 board) Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds G
MTB75N05HD
Motorola Preferred Device
TMOS POWER FET 75 AMPERES 50 VOLTS RDS(on) = 9.5 m
TM
D
CASE 418B-02, Style 2 D2PAK S
Symbol VDSS VDGR VGS ID ID IDM PD
Value 50 50 20 75 65 225 125 1.0 2.5 - 55 to 150 500 1.0 62.5 50 260
Unit Volts
Amps
Watts W/C Watts C mJ C/W
TJ, Tstg EAS RJC RJA RJA TL
C
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
Designer's, E-FET and HDTMOS are trademarks of Motorola Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value. REV 2
(c)Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1995
1
MTB75N05HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 50 V, VGS = 0) (VDS = 50 V, VGS = 0, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance(3) (VGS = 10 Vdc, ID = 20 Adc) Drain-to-Source On-Voltage (VGS = 10 Vdc)(3) (ID = 75 A) (ID = 20 Adc, TJ = 125C) Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 40 V, ID = 75 A, VGS = 10 V) (VDD = 25 V, ID = 75 A, VGS = 10 V, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 75 A, VGS = 0) (Cpk 10)(2) (IS = 20 A, VGS = 0) (IS = 20 A, VGS = 0, TJ = 125C) VSD -- -- trr (IS = 37.5 A, VGS = 0, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) (2) (3) (4) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. Reflects Typical Values. Cpk = ABSOLUTE VALUE OF (SPEC - AVG) / 3 * SIGMA). For accurate measurements, good Kelvin contact required. Switching characteristics are independent of operating junction temperature. LD -- -- LS -- 7.5 -- 3.5 4.5 -- -- nH ta tb QRR -- -- -- -- 0.97 0.80 0.68 57 40 17 0.17 -- 1.00 -- -- -- -- -- C Vdc -- -- -- -- -- -- -- -- 15 170 70 100 71 13 33 26 30 340 140 200 100 -- -- -- nC ns (VDS = 25 V, VGS = 0, (Cpk 2.0)(2) f = 1.0 MHz) (Cpk 2.0)(2) (Cpk 2.0)(2) Ciss Coss Crss -- -- -- 2600 1000 230 2900 1100 275 pF (Cpk 1.5)(2) VGS(th) 2.0 -- (Cpk 3.0)(2) RDS(on) -- VDS(on) -- -- gFS 15 0.63 -- -- -- 0.34 -- mhos 7.0 9.5 Vdc -- 6.3 4.0 -- Vdc mV/C m (Cpk 2)(2) V(BR)DSS 50 -- IDSS -- -- IGSS -- -- 100 -- -- 10 100 nAdc -- 54.9 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit
Reverse Recovery Time
ns
2
Motorola TMOS Power MOSFET Transistor Device Data
MTB75N05HD
TYPICAL ELECTRICAL CHARACTERISTICS(1)
160 140 I D , DRAIN CURRENT (AMPS) 120 100 80 60 40 20 0 0 0.5 1 1.5 2 5V 2.5 3 3.5 4 4.5 5 6V VGS = 10 V 7V TJ = 25C I D , DRAIN CURRENT (AMPS) 160 140 120 100 80 60 40 20 0 0 1 2 3 4 5 100C TJ = - 55C 25C 6 7 8
VDS 10 V
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.014 VGS = 10 V 0.012 TJ = 100C 0.01 0.008 0.006 0.004 0.002 25C
0.009 TJ = 25C 0.008
VGS = 10 V
0.007 15 V 0.006
- 55C
0.005 0 20 40 60 80 100 120 140 160 ID, DRAIN CURRENT (AMPS)
0
20
40
60
80
100
120
140
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Drain Current and Temperature
Figure 4. On-Resistance versus Drain Current and Gate Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
2 VGS = 10 V ID = 37.5 A
10000 VGS = 0 V 1000 TJ = 125C
I DSS, LEAKAGE (nA)
1.5
1
100
100C
0.5
10 25C
0 - 50
0 - 25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45 50 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
(1)Pulse Tests: Pulse Width 250 s, Duty Cycle 2%.
Figure 6. Drain-To-Source Leakage Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
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MTB75N05HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in a RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
8000 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 10 5 VGS 0 VDS 5 Crss Ciss Coss Crss 10 15 20 25 Ciss
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board-mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
VDS = 0
VGS = 0
TJ = 25C
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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Motorola TMOS Power MOSFET Transistor Device Data
MTB75N05HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 0 Q3 25 50 QG, TOTAL GATE CHARGE (nC) VDS Q1 Q2 TJ = 25C ID = 75 A QT VGS 40 30 20 10 0 75 60 50 1000 TJ = 25C ID = 75 A VDD = 35 V VGS = 10 V 100 t, TIME (ns) td(off) tf tr VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
10
td(on)
1 1 10 RG, GATE RESISTANCE (OHMS) 100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short t rr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high
80
di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to Motorola standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
40 di/dt = 300 A/s 30 I S , SOURCE CURRENT (AMPS) 20 10 0 - 10 - 20 - 30 STANDARD CELL DENSITY trr HIGH CELL DENSITY trr tb ta
TJ = 25C 70 VGS = 0 V 60 50
I S , SOURCE CURRENT (AMPS)
40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
- 40 - 120 - 100 - 80 - 60
- 40 - 20 0 t, TIME (ns)
20
40
60
80
Figure 10. Diode Forward Voltage versus Current
Figure 11. Reverse Recovery Time (trr)
Motorola TMOS Power MOSFET Transistor Device Data
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MTB75N05HD
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
1000 10 s EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
500 450 400 350 300 250 200 150 100 50 0 25 ID = 75 A
100
10
100 s 1 ms 10 ms dc
1
RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT
0.1 0.1
1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
100
150 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)
175
Figure 12. Maximum Rated Forward Biased Safe Operating Area
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature
1 D = 0.5
0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E- 05 1.0E- 04 1.0E- 03 1.0E- 02 t, TIME (s) 1.0E- 01 1.0E+00 1.0E+01 t1 P(pk) RJC(t) = r(t) RJC RJC = 1.0C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)
t2 DUTY CYCLE, D = t1/t2
Figure 14. Thermal Response
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Motorola TMOS Power MOSFET Transistor Device Data
MTB75N05HD
3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25
RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils
50
75
100
125
150
TA, AMBIENT TEMPERATURE (C)
Figure 15. D2PAK Power Derating Curve
PACKAGE DIMENSIONS
C E B
4
V
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 14.60 15.88 1.14 1.40
A
1 2 3
S
STYLE 2: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN
-T-
SEATING PLANE
K G D H
3 PL M
J
DIM A B C D E G H J K S V
0.13 (0.005)
T
CASE 418B-02 ISSUE B
Motorola TMOS Power MOSFET Transistor Device Data
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MTB75N05HD
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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Motorola TMOS Power MOSFET Transistor Device Data MTB75N05HD/D
*MTB75N05HD/D*

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